Rapidly changing supply currents in digital circuits may induce noise onto the power supply lines and cause other problems. One technique to avoid this induced noise is to place capacitors, connected between the power supply traces and ground, physically near to those elements within the digital circuits that mar, require rapidly changing supply currents. Capacitors used in this manner are called decoupling capacitors or bypass capacitors. These are used in circuit designs as a means of supplying a low-impedance source of current when rapidly changing supply current is demanded by other elements of the circuit. Another viewpoint of decoupling capacitors is that they filter noise on the power supply lines.
Designers have various options when using decoupling capacitors on printed wiring boards. A mixture of high-capacitance electrolytic capacitors to suppress low-frequency changes and small-capacitance mica or ceramic capacitors to suppress high-frequency changes is commonly used. However, when placing decoupling capacitors on an integrated circuit, the capacitors, as with other circuit elements such as the resistors, must be fabricated from silicon, doped silicon, and deposited metal.
One common method uses the gate capacitance inherent in a metal-oxide-semiconductor (MOS) transistor as the decoupling capacitor. For example, a standard enhancement-mode p-type MOS (PMOS) device, well-known in the art, may be used. In one configuration, the gate electrode is connected to the negative Vss connections and the drain, source, and substrate electrodes are connected to the positive Vcc connections. This configuration, called a “strong inversion” mode, was successfully used in integrated circuits until quite recently. Then, as gate oxide layers became thinner, the leakage current through the gate oxide became substantial. In another configuration, the drain, source, and substrate electrodes are connected to the negative Vss connections and the gate electrode is connected to the positive Vcc connections. This configuration, called a “depletion” mode, avoids the leakage through the gate oxide but has poor capacitance to voltage characteristics.